
State Machine - |init_pwr_up_fpga|i2c_master_top:I2C|i2c_master_byte_ctrl:byte_controller|c_state
Name c_state.ST_IDLE c_state.ST_STOP c_state.ST_ACK c_state.ST_WRITE c_state.ST_READ c_state.ST_START 
c_state.ST_IDLE 0 0 0 0 0 0 
c_state.ST_START 1 0 0 0 0 1 
c_state.ST_READ 1 0 0 0 1 0 
c_state.ST_WRITE 1 0 0 1 0 0 
c_state.ST_ACK 1 0 1 0 0 0 
c_state.ST_STOP 1 1 0 0 0 0 

State Machine - |init_pwr_up_fpga|USB_I2C_state_machine:usb_i2c_sm|c_state
Name c_state.DELAY c_state.I2C_get_last_byte c_state.I2C_RD_TBT_last c_state.I2C_RD_CR_last c_state.I2C_RD_stop_flag c_state.I2C_WR_TBT_last c_state.I2C_WR_CR_last c_state.I2C_WR_TXR_last c_state.I2C_WR_stop_flag c_state.I2C_WR_TBT_first c_state.I2C_WR_CR_first c_state.I2C_WR_TXR_first c_state.LOAD_CTR c_state.LOAD_PRER_HI c_state.LOAD_PRER_LO c_state.IDLE 
c_state.IDLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
c_state.LOAD_PRER_LO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
c_state.LOAD_PRER_HI 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
c_state.LOAD_CTR 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
c_state.I2C_WR_TXR_first 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
c_state.I2C_WR_CR_first 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
c_state.I2C_WR_TBT_first 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
c_state.I2C_WR_stop_flag 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
c_state.I2C_WR_TXR_last 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
c_state.I2C_WR_CR_last 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
c_state.I2C_WR_TBT_last 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
c_state.I2C_RD_stop_flag 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
c_state.I2C_RD_CR_last 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
c_state.I2C_RD_TBT_last 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
c_state.I2C_get_last_byte 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
c_state.DELAY 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
