TX_10G_PLL |

2018.10.26.15:47:30 | Datasheet

Overview

Memory Map

## xcvr_atx_pll_a10_0

altera_xcvr_atx_pll_a10 v18.1

## Parameters
rcfg_debug | 0
enable_pll_reconfig | 0
enable_advanced_avmm_options | 0
rcfg_jtag_enable | 0
rcfg_separate_avmm_busy | 0
rcfg_enable_avmm_busy_port | 0
set_capability_reg_enable | 0
set_user_identifier | 0
set_csr_soft_logic_enable | 0
dbg_embedded_debug_enable | 0
dbg_capability_reg_enable | 0
dbg_user_identifier | 0
dbg_stat_soft_logic_enable | 0
dbg_ctrl_soft_logic_enable | 0
rcfg_file_prefix | altera_xcvr_atx_pll_a10
rcfg_sv_file_enable | 0
rcfg_h_file_enable | 0
rcfg_txt_file_enable | 0
rcfg_mif_file_enable | 0
rcfg_multi_enable | 0
set_rcfg_emb_strm_enable | 0
rcfg_emb_strm_enable | 0
rcfg_reduced_files_enable | 0
rcfg_profile_cnt | 2
rcfg_profile_select | 1
rcfg_profile_data0 |
rcfg_profile_data1 |
rcfg_profile_data2 |
rcfg_profile_data3 |
rcfg_profile_data4 |
rcfg_profile_data5 |
rcfg_profile_data6 |
rcfg_profile_data7 |
rcfg_params | rcfg_debug,enable_pll_reconfig,rcfg_jtag_enable,rcfg_separate_avmm_busy,rcfg_enable_avmm_busy_port,set_capability_reg_enable,set_user_identifier,set_csr_soft_logic_enable,enable_pld_atx_cal_busy_port,support_mode,prot_mode,bw_sel,refclk_cnt,refclk_index,primary_pll_buffer,enable_8G_path,enable_16G_path,enable_pcie_clk,enable_cascade_out,enable_hip_cal_done_port,set_hip_cal_en,set_output_clock_frequency,set_auto_reference_clock_frequency,set_manual_reference_clock_frequency,set_fref_clock_frequency,set_m_counter,set_ref_clk_div,set_l_counter,set_l_cascade_counter,set_l_cascade_predivider,set_k_counter,enable_mcgb,mcgb_div,enable_hfreq_clk,enable_mcgb_pcie_clksw,mcgb_aux_clkin_cnt,enable_bonding_clks,enable_fb_comp_bonding,pma_width,enable_pld_mcgb_cal_busy_port
rcfg_param_labels | rcfg_debug,Enable dynamic reconfiguration,Enable Altera Debug Master Endpoint,Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE,Enable avmm_busy port,Enable capability registers,Set user-defined IP identifier,Enable control and status registers,enable_pld_atx_cal_busy_port,Support mode,Protocol mode,Bandwidth,Number of PLL reference clocks,Selected reference clock source,Primary PLL clock output buffer,Enable PLL GX clock output port,Enable PLL GT clock output port,Enable PCIe clock output port,Enable cascade clock output port,Enable calibration status ports for HIP,Enable PCIe hard IP calibration,PLL output frequency,PLL integer reference clock frequency,PLL fractional reference clock frequency,PLL fractional reference clock frequency,Multiply factor (M-Counter),Divide factor (N-Counter),Divide factor (L-Counter),Divide factor (L-Cascade Counter),predivide factor (L-Cascade Predivider),Fractional multiply factor (K),Include Master Clock Generation Block,Clock division factor,Enable x6/xN non-bonded high-speed clock output port,Enable PCIe clock switch interface,Number of auxiliary MCGB clock input ports.,Enable bonding clock output ports,Enable feedback compensation bonding,PMA interface width,enable_pld_mcgb_cal_busy_port
rcfg_param_vals0 |
rcfg_param_vals1 |
rcfg_param_vals2 |
rcfg_param_vals3 |
rcfg_param_vals4 |
rcfg_param_vals5 |
rcfg_param_vals6 |
rcfg_param_vals7 |
hssi_pma_lc_refclk_select_mux_powerdown_mode | powerup
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch0_src | scratch0_src_lvpecl
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch1_src | scratch1_src_lvpecl
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch2_src | scratch2_src_lvpecl
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch3_src | scratch3_src_lvpecl
hssi_pma_lc_refclk_select_mux_xmux_lc_scratch4_src | scratch4_src_lvpecl
hssi_pma_lc_refclk_select_mux_xmux_refclk_src | src_lvpecl
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_iqclk_sel | power_down
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch0_src | scratch0_power_down
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch1_src | scratch1_power_down
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch2_src | scratch2_power_down
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch3_src | scratch3_power_down
hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch4_src | scratch4_power_down
hssi_pma_lc_refclk_select_mux_refclk_select | ref_iqclk0
hssi_pma_lc_refclk_select_mux_silicon_rev | 20nm1
hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping | ref_iqclk0
hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping | power_down
hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping | power_down
hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping | power_down
hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping | power_down
hssi_refclk_divider_silicon_rev | 20nm1
hssi_refclk_divider_clk_divider | div2_off
hssi_refclk_divider_core_clk_lvpecl | core_clk_lvpecl_off
hssi_refclk_divider_enable_lvpecl | lvpecl_enable
hssi_refclk_divider_optimal | true
hssi_refclk_divider_powerdown_mode | powerup
hssi_refclk_divider_sel_pldclk | iqclk_sel_lvpecl
hssi_refclk_divider_sup_mode | user_mode
hssi_refclk_divider_term_tristate | tristate_off
hssi_refclk_divider_vcm_pup | pup_off
hssi_refclk_divider_clkbuf_sel | high_vcm
hssi_refclk_divider_iostandard | lvpecl
atx_pll_silicon_rev | 20nm1
atx_pll_is_cascaded_pll | false
atx_pll_cgb_div | 1
atx_pll_pma_width | 64
atx_pll_lc_atb | atb_selectdisable
atx_pll_cp_compensation_enable | true
atx_pll_cp_current_setting | cp_current_setting33
atx_pll_cp_testmode | cp_normal
atx_pll_cp_lf_3rd_pole_freq | lf_3rd_pole_setting0
atx_pll_lf_cbig_size | lf_cbig_setting4
atx_pll_cp_lf_order | lf_2nd_order
atx_pll_lf_resistance | lf_setting1
atx_pll_lf_ripplecap | lf_no_ripple
atx_pll_cal_status | cal_in_progress
atx_pll_bonding | pll_bonding
atx_pll_expected_lc_boost_voltage | 0
atx_pll_power_rail_et | 950
atx_pll_dprio_lc_vreg_boost_scratch | 0
atx_pll_dprio_lc_vreg1_boost_scratch | 0
atx_pll_dprio_clk_vreg_boost_scratch | 0
atx_pll_dprio_mcgb_vreg_boost_scratch | 0
atx_pll_dprio_vreg_boost_step_size | 0
atx_pll_dprio_vreg1_boost_step_size | 0
atx_pll_dprio_clk_vreg_boost_step_size | 0
atx_pll_dprio_mcgb_vreg_boost_step_size | 0
atx_pll_dprio_lc_vreg_boost_expected_voltage | 0
atx_pll_dprio_lc_vreg1_boost_expected_voltage | 0
atx_pll_dprio_clk_vreg_boost_expected_voltage | 0
atx_pll_dprio_mcgb_vreg_boost_expected_voltage | 0
atx_pll_clk_high_perf_voltage | 0
atx_pll_clk_mid_power_voltage | 0
atx_pll_clk_low_power_voltage | 0
atx_pll_tank_sel | lctank1
atx_pll_tank_band | lc_band4
atx_pll_tank_voltage_coarse | vreg_setting_coarse0
atx_pll_tank_voltage_fine | vreg_setting5
atx_pll_output_regulator_supply | vreg1v_setting0
atx_pll_overrange_voltage | over_setting0
atx_pll_underrange_voltage | under_setting4
atx_pll_fb_select | direct_fb
atx_pll_d2a_voltage | d2a_setting_4
atx_pll_dsm_mode | dsm_mode_integer
atx_pll_dsm_out_sel | pll_dsm_disable
atx_pll_dsm_ecn_bypass | false
atx_pll_dsm_ecn_test_en | false
atx_pll_dsm_fractional_division | 1
atx_pll_dsm_fractional_value_ready | pll_k_ready
atx_pll_enable_lc_calibration | true
atx_pll_enable_lc_vreg_calibration | true
atx_pll_iqclk_mux_sel | iqtxrxclk0
atx_pll_vco_bypass_enable | false
atx_pll_l_counter | 2
atx_pll_l_counter_enable | true
atx_pll_cascadeclk_test | cascadetest_off
atx_pll_hclk_divide | 1
atx_pll_enable_hclk | hclk_disabled
atx_pll_m_counter | 16
atx_pll_ref_clk_div | 1
atx_pll_bandwidth_range_high | 0 hz
atx_pll_bandwidth_range_low | 0 hz
atx_pll_bw_sel | high
atx_pll_calibration_mode | cal_off
atx_pll_datarate | 10240000000 bps
atx_pll_device_variant | device1
atx_pll_f_max_pfd | 800000000 Hz
atx_pll_f_max_ref | 800000000 Hz
atx_pll_f_max_tank_0 | 8800000000 Hz
atx_pll_f_max_tank_1 | 11400000000 Hz
atx_pll_f_max_tank_2 | 14400000000 Hz
atx_pll_f_max_vco | 14400000000 Hz
atx_pll_f_max_x1 | 8700000000 Hz
atx_pll_f_min_pfd | 61440000 Hz
atx_pll_f_min_ref | 61440000 Hz
atx_pll_f_min_tank_0 | 6500000000 Hz
atx_pll_f_min_tank_1 | 8800000000 Hz
atx_pll_f_min_tank_2 | 11400000000 Hz
atx_pll_f_min_vco | 7200000000 Hz
atx_pll_initial_settings | true
atx_pll_l_counter_scratch | 1
atx_pll_lc_mode | lccmu_normal
atx_pll_n_counter_scratch | 1
atx_pll_output_clock_frequency | 5120000000 Hz
atx_pll_power_mode | low_power
atx_pll_powerdown_mode | powerup
atx_pll_prot_mode | basic_tx
atx_pll_reference_clock_frequency | 320000000 Hz
atx_pll_side | side_unknown
atx_pll_pm_speed_grade | e4
atx_pll_sup_mode | user_mode
atx_pll_top_or_bottom | tb_unknown
atx_pll_vccdreg_clk | vreg_clk5
atx_pll_vccdreg_fb | vreg_fb8
atx_pll_vccdreg_fw | vreg_fw5
atx_pll_regulator_bypass | reg_enable
atx_pll_vco_freq | 10240000000 Hz
atx_pll_f_max_vco_fractional | 0 hz
atx_pll_f_max_pfd_fractional | 0 hz
atx_pll_min_fractional_percentage | 0
atx_pll_max_fractional_percentage | 100
atx_pll_analog_mode | user_custom
atx_pll_is_otn | false
atx_pll_is_sdi | false
atx_pll_primary_use | hssi_x1
atx_pll_fpll_refclk_selection | select_vco_output
atx_pll_lc_to_fpll_l_counter_scratch | 1
atx_pll_lc_to_fpll_l_counter | lcounter_setting0
atx_pll_pfd_delay_compensation | normal_delay
atx_pll_xcpvco_xchgpmplf_cp_current_boost | normal_setting
atx_pll_f_max_lcnt_fpll_cascading | 1200000000
atx_pll_pfd_pulse_width | pulse_width_setting0
atx_pll_enable_idle_atx_pll_support | idle_none
enable_advanced_options | 0
enable_hip_options | 0
enable_manual_configuration | 1
generate_docs | 0
generate_add_hdl_instance_example | 0
device_family | ARRIA10
device | 10AX016E4F27E3LG
base_device | NIGHTFURY1
test_mode | 0
enable_pld_atx_cal_busy_port | 1
enable_debug_ports_parameters | 0
support_mode | user_mode
message_level | error
pma_speedgrade | e4
device_revision | 20nm1
prot_mode | Basic
prot_mode_fnl | basic_tx
primary_use | hssi_x1
bw_sel | high
refclk_cnt | 1
refclk_index | 0
silicon_rev | false
fb_select_fnl | direct_fb
primary_pll_buffer | GX clock output buffer
enable_8G_buffer_fnl | true
enable_16G_buffer_fnl | false
enable_8G_path | 1
enable_16G_path | 0
enable_pcie_clk | 0
enable_cascade_out | 0
enable_atx_to_fpll_cascade_out | 0
enable_hip_cal_done_port | 0
set_hip_cal_en | 0
hip_cal_en | disable
dsm_mode | dsm_mode_integer
set_output_clock_frequency | 5120.0
output_clock_datarate | 10240.0
output_clock_frequency | 5120.0 MHz
vco_freq | 10240.0 MHz
datarate | 10240.0 Mbps
enable_fractional | 0
set_auto_reference_clock_frequency | 320.0
set_manual_reference_clock_frequency | 200.0
reference_clock_frequency_fnl | 320.000000 MHz
set_fref_clock_frequency | 156.25
feedback_clock_frequency_fnl | 156.25
select_manual_config | false
m_counter | 16
effective_m_counter | 1
set_m_counter | 24
ref_clk_div | 1
set_ref_clk_div | 1
l_counter | 2
set_l_counter | 16
l_cascade_counter | 1
set_l_cascade_counter | 15
l_cascade_predivider | 1
set_l_cascade_predivider | 1
k_counter | 1
set_k_counter | 2000000000
auto_list | 61.686747 {m 83 effective_m 83 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 62.439024 {m 82 effective_m 82 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 63.209877 {m 81 effective_m 81 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 64.000000 {m 80 effective_m 80 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 64.810127 {m 79 effective_m 79 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 65.641026 {m 78 effective_m 78 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 66.493506 {m 77 effective_m 77 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 67.368421 {m 76 effective_m 76 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 68.266667 {m 75 effective_m 75 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 69.189189 {m 74 effective_m 74 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 70.136986 {m 73 effective_m 73 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 71.111111 {m 72 effective_m 72 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 72.112676 {m 71 effective_m 71 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 73.142857 {m 70 effective_m 70 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 74.202899 {m 69 effective_m 69 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 75.294118 {m 68 effective_m 68 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 76.417910 {m 67 effective_m 67 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 77.575758 {m 66 effective_m 66 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 78.769231 {m 65 effective_m 65 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 80.000000 {m 64 effective_m 64 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 81.269841 {m 63 effective_m 63 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 82.580645 {m 62 effective_m 62 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 83.934426 {m 61 effective_m 61 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 85.333333 {m 60 effective_m 60 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 86.779661 {m 59 effective_m 59 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 88.275862 {m 58 effective_m 58 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 89.824561 {m 57 effective_m 57 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 91.428571 {m 56 effective_m 56 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 93.090909 {m 55 effective_m 55 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 94.814815 {m 54 effective_m 54 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 96.603774 {m 53 effective_m 53 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 98.461538 {m 52 effective_m 52 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 100.392157 {m 51 effective_m 51 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 102.400000 {m 50 effective_m 50 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 104.489796 {m 49 effective_m 49 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 106.666667 {m 48 effective_m 48 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 108.936170 {m 47 effective_m 47 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 111.304348 {m 46 effective_m 46 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 113.777778 {m 45 effective_m 45 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 116.363636 {m 44 effective_m 44 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 119.069767 {m 43 effective_m 43 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 121.904762 {m 42 effective_m 42 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 123.373494 {m 83 effective_m 83 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 124.878049 {m 41 effective_m 41 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 126.419753 {m 81 effective_m 81 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 128.000000 {m 40 effective_m 40 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 129.620253 {m 79 effective_m 79 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 131.282051 {m 39 effective_m 39 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 132.987013 {m 77 effective_m 77 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 134.736842 {m 38 effective_m 38 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 136.533333 {m 75 effective_m 75 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 138.378378 {m 37 effective_m 37 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 140.273973 {m 73 effective_m 73 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 142.222222 {m 36 effective_m 36 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 144.225352 {m 71 effective_m 71 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 146.285714 {m 35 effective_m 35 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 148.405797 {m 69 effective_m 69 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 150.588235 {m 34 effective_m 34 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 152.835821 {m 67 effective_m 67 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 155.151515 {m 33 effective_m 33 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 157.538462 {m 65 effective_m 65 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 160.000000 {m 32 effective_m 32 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 162.539683 {m 63 effective_m 63 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 165.161290 {m 31 effective_m 31 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 167.868852 {m 61 effective_m 61 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 170.666667 {m 30 effective_m 30 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 173.559322 {m 59 effective_m 59 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 176.551724 {m 29 effective_m 29 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 179.649123 {m 57 effective_m 57 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 182.857143 {m 28 effective_m 28 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 186.181818 {m 55 effective_m 55 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 189.629630 {m 27 effective_m 27 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 193.207547 {m 53 effective_m 53 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 196.923077 {m 26 effective_m 26 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 200.784314 {m 51 effective_m 51 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 204.800000 {m 25 effective_m 25 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 208.979592 {m 49 effective_m 49 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 213.333333 {m 24 effective_m 24 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 217.872340 {m 47 effective_m 47 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 222.608696 {m 23 effective_m 23 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 227.555556 {m 45 effective_m 45 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 232.727273 {m 22 effective_m 22 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 238.139535 {m 43 effective_m 43 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 243.809524 {m 21 effective_m 21 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 246.746988 {m 83 effective_m 83 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 249.756098 {m 41 effective_m 41 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 252.839506 {m 81 effective_m 81 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 256.000000 {m 20 effective_m 20 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 259.240506 {m 79 effective_m 79 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 262.564103 {m 39 effective_m 39 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 265.974026 {m 77 effective_m 77 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 269.473684 {m 19 effective_m 19 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 273.066667 {m 75 effective_m 75 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 276.756757 {m 37 effective_m 37 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 280.547945 {m 73 effective_m 73 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 284.444444 {m 18 effective_m 18 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 288.450704 {m 71 effective_m 71 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 292.571429 {m 35 effective_m 35 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 296.811594 {m 69 effective_m 69 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 301.176471 {m 17 effective_m 17 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 305.671642 {m 67 effective_m 67 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 310.303030 {m 33 effective_m 33 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 315.076923 {m 65 effective_m 65 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 320.000000 {m 16 effective_m 16 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 325.079365 {m 63 effective_m 63 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 330.322581 {m 31 effective_m 31 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 335.737705 {m 61 effective_m 61 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 341.333333 {m 15 effective_m 15 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 347.118644 {m 59 effective_m 59 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 353.103448 {m 29 effective_m 29 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 359.298246 {m 57 effective_m 57 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 365.714286 {m 14 effective_m 14 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 372.363636 {m 55 effective_m 55 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 379.259259 {m 27 effective_m 27 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 386.415094 {m 53 effective_m 53 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 393.846154 {m 13 effective_m 13 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 401.568627 {m 51 effective_m 51 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 409.600000 {m 25 effective_m 25 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 417.959184 {m 49 effective_m 49 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 426.666667 {m 12 effective_m 12 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 435.744681 {m 47 effective_m 47 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 445.217391 {m 23 effective_m 23 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 455.111111 {m 45 effective_m 45 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 465.454545 {m 11 effective_m 11 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 476.279070 {m 43 effective_m 43 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 487.619048 {m 21 effective_m 21 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 493.493976 {m 83 effective_m 83 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 499.512195 {m 41 effective_m 41 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 505.679012 {m 81 effective_m 81 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 512.000000 {m 10 effective_m 10 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 518.481013 {m 79 effective_m 79 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 525.128205 {m 39 effective_m 39 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 531.948052 {m 77 effective_m 77 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 538.947368 {m 19 effective_m 19 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 546.133333 {m 75 effective_m 75 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 553.513514 {m 37 effective_m 37 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 561.095890 {m 73 effective_m 73 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 568.888889 {m 9 effective_m 9 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 576.901408 {m 71 effective_m 71 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 585.142857 {m 35 effective_m 35 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 593.623188 {m 69 effective_m 69 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 602.352941 {m 17 effective_m 17 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 611.343284 {m 67 effective_m 67 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 620.606061 {m 33 effective_m 33 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 630.153846 {m 65 effective_m 65 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 640.000000 {m 8 effective_m 8 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 650.158730 {m 63 effective_m 63 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 660.645161 {m 31 effective_m 31 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 671.475410 {m 61 effective_m 61 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 682.666667 {m 15 effective_m 15 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 694.237288 {m 59 effective_m 59 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 706.206897 {m 29 effective_m 29 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 718.596491 {m 57 effective_m 57 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 731.428571 {m 14 effective_m 14 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 744.727273 {m 55 effective_m 55 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 758.518519 {m 27 effective_m 27 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 772.830189 {m 53 effective_m 53 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 787.692308 {m 13 effective_m 13 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0}
manual_list |
pll_setting | refclk {320.000000 MHz} m_cnt 16 n_cnt 1 l_cnt 2 k_cnt 1 l_cascade 1 l_cascade_predivider 1 outclk {5120.0 MHz}
enable_fb_comp_bonding_fnl | 0
check_output_ports_pll | 0
iqclk_mux_sel | iqtxrxclk0
set_altera_xcvr_atx_pll_a10_calibration_en | 1
calibration_en | enable
enable_analog_resets | 0
enable_ext_lockdetect_ports | 0
atx_pll_bonding_mode | cpri_bonding
lc_refclk_select | 0
enable_mcgb | 0
mcgb_div | 1
mcgb_div_fnl | 1
enable_hfreq_clk | 0
enable_mcgb_pcie_clksw | 0
mcgb_aux_clkin_cnt | 0
mcgb_in_clk_freq | 5120.0
mcgb_out_datarate | 10240.0
enable_bonding_clks | 0
enable_fb_comp_bonding | 0
mcgb_enable_iqtxrxclk | disable_iqtxrxclk
pma_width | 64
enable_mcgb_debug_ports_parameters | 0
enable_pld_mcgb_cal_busy_port | 0
check_output_ports_mcgb | 0
is_protocol_PCIe | 0
mapped_output_clock_frequency | 5120.0 MHz
mapped_primary_pll_buffer | GX clock output buffer
mapped_hip_cal_done_port | 0
hssi_pma_cgb_master_prot_mode | basic_tx
hssi_pma_cgb_master_silicon_rev | 20nm1
hssi_pma_cgb_master_x1_div_m_sel | divbypass
hssi_pma_cgb_master_cgb_enable_iqtxrxclk | disable_iqtxrxclk
hssi_pma_cgb_master_ser_mode | sixty_four_bit
hssi_pma_cgb_master_datarate | 10240000000 bps
hssi_pma_cgb_master_cgb_power_down | normal_cgb
hssi_pma_cgb_master_observe_cgb_clocks | observe_nothing
hssi_pma_cgb_master_op_mode | enabled
hssi_pma_cgb_master_tx_ucontrol_reset_pcie | pcscorehip_controls_mcgb
hssi_pma_cgb_master_vccdreg_output | vccdreg_nominal
hssi_pma_cgb_master_input_select | lcpll_top
hssi_pma_cgb_master_input_select_gen3 | unused
gui_parameter_list | K counter (valid in fractional mode),L counter (valid in non-cascade mode),M counter,N counter,L cascade predivider/VCO divider(valid in cascade mode) ,L cascade counter (valid in cascade mode),PLL output frequency,vco_freq,datarate
gui_parameter_values | 1,2,16,1,select_vco_output,1,5120.0 MHz,10240.0 MHz,10240.0 Mbps
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

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