| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| AD9508_1 |
27 |
0 |
1 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC121_dp1|altsyncram_component|auto_generated |
35 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ADC121_dp1 |
35 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| dos1 |
71 |
0 |
58 |
0 |
53 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C|byte_controller|bit_controller |
27 |
2 |
0 |
2 |
8 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| I2C|byte_controller |
35 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C |
19 |
1 |
0 |
1 |
12 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| usb_i2c_sm |
652 |
0 |
0 |
0 |
656 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| dac1 |
60 |
0 |
3 |
0 |
54 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| dpm2|altsyncram_component|auto_generated |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| dpm2 |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|wrfull_eq_comp_msb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|wrfull_eq_comp_lsb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|wrfull_eq_comp1_msb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|rdempty_eq_comp_msb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|rdempty_eq_comp_lsb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|rdempty_eq_comp1_msb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|ws_dgrp|dffpipe17 |
7 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|ws_dgrp |
7 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|rs_dgwp|dffpipe12 |
7 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|rs_dgwp |
7 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|fifo_ram |
29 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|wrptr_g1p |
2 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated|rdptr_g1p |
2 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk|dcfifo_component|auto_generated |
18 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650b_clk |
18 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pll_3|altpll_component|auto_generated |
3 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pll_3 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| dpm1|altsyncram_component|auto_generated |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| dpm1 |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|wrfull_eq_comp_msb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|wrfull_eq_comp_lsb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|wrfull_eq_comp1_msb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|rdempty_eq_comp_msb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|rdempty_eq_comp_lsb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|rdempty_eq_comp1_msb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|ws_dgrp|dffpipe17 |
7 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|ws_dgrp |
7 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|rs_dgwp|dffpipe12 |
7 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|rs_dgwp |
7 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|fifo_ram |
29 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|wrptr_g1p |
2 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated|rdptr_g1p |
2 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk|dcfifo_component|auto_generated |
18 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| AD9650a_clk |
18 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pll_2|altpll_component|auto_generated |
3 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pll_2 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h3|h2|altsyncram_component|auto_generated |
54 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h3|h2 |
54 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h3|h1|altsyncram_component|auto_generated|mux3 |
90 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h3|h1|altsyncram_component|auto_generated|wren_decode_a |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h3|h1|altsyncram_component|auto_generated|rden_decode_b |
2 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h3|h1|altsyncram_component|auto_generated|decode2 |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h3|h1|altsyncram_component|auto_generated |
55 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h3|h1 |
55 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h3|hit_comp_2|LPM_COMPARE_component|auto_generated |
45 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h3|hit_comp_2 |
45 |
22 |
0 |
22 |
1 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| h3|hit_comp_1|LPM_COMPARE_component|auto_generated |
45 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h3|hit_comp_1 |
45 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h3 |
53 |
0 |
2 |
0 |
59 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h2|h2|altsyncram_component|auto_generated |
54 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h2|h2 |
54 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h2|h1|altsyncram_component|auto_generated|mux3 |
90 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h2|h1|altsyncram_component|auto_generated|wren_decode_a |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h2|h1|altsyncram_component|auto_generated|rden_decode_b |
2 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h2|h1|altsyncram_component|auto_generated|decode2 |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h2|h1|altsyncram_component|auto_generated |
55 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h2|h1 |
55 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h2|hit_comp_2|LPM_COMPARE_component|auto_generated |
45 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h2|hit_comp_2 |
45 |
22 |
0 |
22 |
1 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| h2|hit_comp_1|LPM_COMPARE_component|auto_generated |
45 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h2|hit_comp_1 |
45 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h2 |
53 |
0 |
2 |
0 |
59 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h1|h2|altsyncram_component|auto_generated |
54 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h1|h2 |
54 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h1|h1|altsyncram_component|auto_generated|mux3 |
90 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h1|h1|altsyncram_component|auto_generated|wren_decode_a |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h1|h1|altsyncram_component|auto_generated|rden_decode_b |
2 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h1|h1|altsyncram_component|auto_generated|decode2 |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h1|h1|altsyncram_component|auto_generated |
55 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h1|h1 |
55 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h1|hit_comp_2|LPM_COMPARE_component|auto_generated |
45 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h1|hit_comp_2 |
45 |
22 |
0 |
22 |
1 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| h1|hit_comp_1|LPM_COMPARE_component|auto_generated |
45 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h1|hit_comp_1 |
45 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| h1 |
53 |
0 |
2 |
0 |
59 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| dp1|altsyncram_component|auto_generated |
39 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| dp1 |
39 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| adc_rx2|ALTDDIO_IN_component|auto_generated |
6 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| adc_rx2 |
6 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| adc_rx1|ALTDDIO_IN_component|auto_generated |
6 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| adc_rx1 |
6 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| FC1 |
323 |
0 |
7 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pll_1|altpll_component|auto_generated |
3 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pll_1 |
2 |
1 |
0 |
1 |
5 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| pll_0|altpll_component|auto_generated |
3 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pll_0 |
2 |
1 |
0 |
1 |
5 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |