Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Git Repositories

Testboard GUI	Source code and usage instructions for the GUI to control the testboard
Testboard Analysis	Scripts for analyzing data taken with testboard, particularly pedestal data and data taken using the onboard pulser

Chip Documentation

The below table contains documentation for most, but not all, of the ASICs on the analog testboard.

Document	Description
datasheet_Lauroc1_20190506.pdf	Documentation for the LAUROC1 pre-amp/shaper. Updated May 6, 2019
COLUTAV2_ds.pdf	Documentation for the COLUTAv2 ADC. Updated February 2, 2019
lpGBT.pdf	Documentation for the low power Giga-Bit Transceiver. Updated April 9, 2019
dac9881.pdf	Documentation for the DAC that provides a voltage to the onboard pulser. Updated September 2016
a10_overview.pdf a10_datasheet.pdf	Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB
Si5345-44-42-D-RM.pdf	Documentation for onboard Si5345 Clock Chip

Presentations

ATLAS Upgrade Week Nov 2019

Board Firmware and Schematic

File	Comment
Analog_Testboard_FPGA_oct2.zip	v1.1 board firmware as of Oct 2, 2019
Analog_Testboard.zip	v1.1 board schematic (.pdf, .pcb, and .sch)

Location of connector to program FPGA configuration memory device shown here.

Board Specific Pages

Board Number	Location
E149372	Nevis
E149373	Saclay
E149374	Nevis
E149375	BNL
E149376	Orsay
E149377	UT Austin

Known Issues

1. DAC Turn On. All DAC settings below a particular turn on point correspond to the same measured test point voltage (7.7-8 mV). Turn on point varies for different boards (typically around 400-600).

Symptom:

2. Even/Odd ADC. All ADCs have a preference for the LSB to have a value of 1, resulting in more odd ADC count values than even. Extent of this preference is very dependent on the values of pots P15 and P16, which control the positive and negative reference voltages of the SAR.

• Should have: VREFN_SAR = 0.1, VREFP_SAR 1.1V
  Symptom:
  
  3. Clock Feedthrough (CFT). Pulses from on board pulser contain an extra injected charge that comes from clock signal passing through analog switch. This "clock feedthrough" does not scale with DAC setting and is not expected to have a shape that is the same as that of the pulse. As a result, all pulses are a sum of the true pulse shape and this CFT offset, distorting the shape and affecting the linearity of the pulse height to DAC setting. This is particularly noticeable at the lowest DAC settings, where the CFT constitutes a significant fraction of the total pulse.
  Symptom:
  
  4. DAC Stuck/Misaligned. When powering up, or occasionally during operation, the DAC will get stuck in a bad operational state. This is indicated by the DAC readback function, which checks the equality of the SPI instruction that is sent and readback. If the following error comes up during data-taking, it is recommended to power cycle the board (resetting the DAC).

Symptom:

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%USERSIG{DanielWilliams - 2019-09-26}%

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